1. Field of the Invention
The present invention relates to a method for stabilizing a semiconductor device of SOI (Semiconductor On Insulator) structure and an SOI semiconductor device stabilized by the method.
2. Description of Related Art
As portable devices have come into wide use, development of LSIs capable of working for a longer time with a single battery power source is highly demanded. Moreover, research and development of SOI-MOSFETs which are expected to operate at high speed and consume less electric power have been proceeding.
In general, reduction of leak current is necessary for realizing less power consumption of the SOI-MOSFETs. Electric power consumed in a stand-by state is as large as several hundred .mu.A at the LSI level, which leads to a serious problem.
Taking a short channel SOI-NMOSFET as an example, operation principle thereof in the stand-by state will be explained with reference to FIGS. 10 and 11.
In the stand-by state of the SOI-NMOSFET, for example, a positive voltage is applied to a drain 4. Accordingly, electrons are drawn from a source 5 and travel to the drain 4 via a channel 11. At this time, the electrons travel through the fine channel 11 of SOI-NMOSFET into the vicinity of the drain where an electric field strength is high, thereby turning to a high energy state. Then the electrons arrived at the drain 4 bring about an impact ionization and generate electron-hole pairs. The electrons newly generated by the impact ionization flow into the drain 4, while holes 12 gather at a lower portion of a surface silicon layer 3 adjacent to the source 5, where potential is low.
A model of a leak current in this stand-by state is shown in an equivalent circuit of FIG. 11. According to FIG. 11, a floating body effect by the impact ionization can be mentioned as a main factor dominant over an off-leak current.
In other words, the electrons discharged from the source 5 become a current Ich. The electrons bring about the impact ionization with a certain probability in the vicinity of the drain 4 and are multiplied by a multiplication coefficient (M-1), thereby turning to a current Ii (a current caused by the electrons generated by the impact ionization). On the other hand, the holes discharged from the drain 4 accumulate at a body 13 (a lower portion of the surface silicon layer). The holes 12 accumulated at the body 13 raise a substrate potential Vbs, i.e., cause the floating body effect.
When the floating body effect is produced and the substrate potential Vbs rises, the threshold voltage Vth of a MOSFET decreases. As a result, a subthreshold current is more liable to flow through the channel 11.
Further, when the substrate potential Vbs rises, a parasitic bipolar effect increases. That is, in an NMOSFET, an NPN type bipolar structure is formed from the source/drain regions and the body 13 lying therebetween. Accordingly, the rise in the body potential causes the electrons to be easily taken out from the source 5, thereby increasing a current Ic flowing into the drain via the body or base of the NPN bipolar transistor. The current Ic flows together with the current Ich and further increase the impact ionization. Thus, the parasitic bipolar effect becomes a factor for a positive feedback with respect to the off-leak current (in FIG. 11, a current Ib is a current caused by the holes generated by the impact ionization and the parasitic bipolar effect, and .beta. is the current gain of the parasitic bipolar effect).
In general, the off-leak current of the MOSFET shows a behavior as shown in FIG. 12.
When a voltage Vds between the drain and the source is small (region I), a threshold voltage of the SOI-NMOSFET controls the leak current.
Further, when the voltage Vds increases a little (region II), the increase in the voltage Vbs and back bias effect, become the dominant factor of the leak current. In short, the parasitic bipolar effect may be increased and the impact ionization may be generated, which increases further the leakage current (the region II).
When the voltage Vds increases further (region III), the impact ionization coupled with the positive feedback originated by the parasitic bipolar transistor, has more dominant effect, so that the leak current increases rapidly.
From the above, mentioned as measures for reduction of the off-leak current are,
1. increasing the threshold voltage, PA0 2. suppressing the parasitic bipolar effect and PA0 3. suppressing the impact ionization.
Conventionally, there have been made various proposals for reduction of the off-leak current. For example, IEEE. SSDM. Tech. Dig., pp627-630, 1995 has proposed a method for intentionally forming a defect in a crystal by Ar ion implantation into a body. The defect introduced by such a method serves as a capturing potential, shortens the life span of carriers and contributes toward suppression of the parasitic bipolar effect and the reduction of the off-leak current.
However, in such an implantation method of Ar ions, the crystal defect is formed in a surface silicon layer of a substrate having the SOI structure, thereby reducing a carrier mobility and a drive current of a transistor. Further, this method is problematic in terms of industrial application because it causes multiplication of fabrication processes and an increase in product costs.
Therefore, a technique which is attempted to introduce the capturing potential by utilizing an electric stress has been proposed (Japanese Unexamined Patent Publication No. HEI 9 (1997)-8259). According to this technique, as shown in FIG. 13, a support substrate 1 is maintained at a temperature of 100 to 200.degree. C., a gate 6, a drain 4 and a source 5 are grounded and a positive voltage is applied to the support substrate 1. Thereby a defect 8 can be caused to be introduced to a channel region 7 by the electric stress. The defect 8 serves as the capturing potential of carriers and results in the reduction of the leak current in the stand-by state. Incidentally, the formation of the defect by the electric stress is checked by a charge bombing method.
However, in such a method as described above, the substrate must be heated up to around 200.degree. C. and the electric stress is applied for several hours. Therefore it is inefficient and difficult to realize industrially. Further, the electric stress is also applied to the front channel region 9. So the defect are formed front channel region 9. Accordingly, the drive current of the transistor may possibly be lowered.